Both bipolar and MOS integrated circuits (ICs) have been shown empirically to be susceptible to soft errors when exposed to radiation of ionized particles, and in particular to penetration of an ionized particle referred to hereinafter as a single-event upset (SEU). A "soft error" is defined as a nondestructive data bit error, as opposed to a "hard error" resulting from permanent damage to the IC by an ionized particle.
ICs that contain memory cells or other forms of latch circuits have been known to be upset by single cosmic ray particles in space, and by various radiation sources in ground-based electronic systems, resulting in soft errors. The basic mechanism for such occurrences has been generally recognized to be the collection of charge created by an ion passing through an integrated transistor. The charge collected from a semiconductor junction (e.g., the buried-layer-substrate junction of a bipolar transistor in the "off" state) may be of sufficient magnitude to change the state of a bistable circuit incorporating the transistor or to produce a transient output of a nonconducting transistor in a logic gate circuit incorporating the transistor.
Soft errors generated in random access memories (RAMs) and other bistable circuits, by single ionizing particles, have been observed in controlled laboratory experiments. These experiments have been performed with a wide range of ions and ion energies, from protons to heavy ions (e.g., krypton) from a cyclotron, van de Graaff, or linear accelerator. For a more detailed introduction to single-event upsets in bipolar transistors, see John A. Zoutendyk, "Modeling of Single-Event Upset in Bipolar Integrated circuits," IEEE Transactions on Nuclear Science, Vol. NS-30, No. 6, December 1983; and John A. Zoutendyk, et al., "Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM," IEEE Transactions on Nuclear Science, Vol. NS-32, No. 6, pp. 4164-4169, December 1985.
Following some further discussion of the problem, a solution will be presented with respect to bipolar transistors in integrated circuits, and more specifically with respect to bipolar transistors fabricated in buried layers of semiconductor material, where the buried-layer-substrate junction is normally reverse biased to prevent possible leakage of current between adjacent transistors, each fabricated in its own buried layer.
Single-particle, soft-error generation in ICs has become an important phenomenon in the pursuit of high-density semiconductor chip technology. Bit errors can be caused by a single energetic ion, e.g., a cosmic-ray ion in space, or an alpha particle from radioactive decay. As transistors contained in IC chips become increasingly smaller, they become more susceptible to soft errors owing to the decrease in the amount of ionized charge required to cause an SEU. In latch circuits, such as RAM cells comprised of two cross-coupled transistors commonly referred to as flip-flops, an energetic ion passing through the transistor that is initially off, may tend to turn off the other transistor which is initially on. That will then drive the transistor that was initially off to a full "on" state, and thus drive the "on" transistor to the "off" state. The result is that the memory cell will flip from one to the other state and introduce a bit error. An SEU error in a flip-flop is thus manifested by a "bit flip." This phenomenon is caused by ions that penetrate an active device and produce ion-induced current, I.sub.s, which causes charge to be collected at the buried-layer-substrate junction. Thus, the current I.sub.s of an ion track can cause an SEU when the ion track is within the buried-layer area of a bipolar transistor. Each ion track may cause an SEU bit error in a flip-flop or other form of latch, such as static RAM chips, and in transistors used in logic networks of gates and inverters, because a transient ion-induced current may trigger a following flip-flop or other form of latch to change its state.
Space charge effects militate against the exact analytical treatment of ion tracks making it necessary to solve SEU problems using numerical computer methods. This situation arises from the nonlinearity of the multidimensional differential equations governing collection of the high-injection charge produced by an ion track. Metal-oxide-semiconductor (MOS) RAMs have also been modeled for single-event upset. See John A. Zoutendyk, et al., "Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips," IEEE Transactions on Nuclear Science, Vol. NS-33, No. 6, pp. 1581-1585, December 1986; and John A. Zoutendyk, et al., "Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained From Model Verification," IEEE Transactions on Nuclear Science, Vol. NS-34, No. 6, pp. 1292-1299, December 1987. In MOS RAMs, only a single charge-collection node is involved during any single event, even though different nodes may be charged during different events. By contrast, in a buried-layer IC construction of bipolar transistors, several nodes may be involved during a single event.